knowit: Parallelism

Parallelism can be

pipeline stalls (an instruction spending more than one clock cycle in a stage)

Instruction Level - Sequential instructions within a program are executed in parallel.

subscalar, operates on and executes one instruction on one or two pieces of data at a time - takes 5 cycles to execute 1 instruction (IF, ID, EX, MEM, WB)
In a superscalar pipeline, multiple instructions are read and passed to a dispatcher, which decides whether or not the instructions can be executed in parallel (simultaneously)

Thread Level (Parallel Computing) - Multiple threads in different processors.

Multiple Instructions-Multiple Data or MIMD
Multi Threading vs Multi Processing
Block Multithreading - Includes context switching
Simultaneous Multithreading - instructions of multiple threads are executed in parallel within one CPU clock cycle

Data Level - Data is divided into parts and different processors execute same instructions on different set of data.

A wait state is a delay experienced by a computer processor when accessing external memory or another device that is slow to respond.

Wait states are a pure waste for a processor's performance. Modern designs try to eliminate or hide them using a variety of techniques: CPU caches, instruction pipelines, instruction prefetch,branch prediction, simultaneous multithreading and others

CPU Cache

Instruction Cache
translation lookaside buffer (TLB) used to speed up virtual-to-physical address translation for both executable instructions and data
Cache Coherence - Communication protocols between the cache managers that keep the data consistent are known as cache coherence protocols
Write-through vs write-back cache
CPU stalls - The time taken to fetch one cache line from memory (read latency) matters because the CPU will run out of things to do while waiting for the cache line. When a CPU reaches this state, it is called a stall.

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